Recently, image drawing devices have been widely installed in appliances such as personal computers, recording/reproducing apparatuses, and broadcasting receiver units. The improvement in processing power of the image drawing device allows the appliance to handle images of higher definition, or display images with higher pixel density, in order to provide more beautiful images to users.
High-definition images require improvements in the performance of image memory (hereinafter, memory) for storage of pixel brightness data, as well as the image drawing device. In particular, an improvement in the speed of a bus that connects between the memory and the image drawing device (regardless of a multi- or single-chip configuration) is important for the improvement in the performance thereof. However, the driving clock of the bus, which is usually slower than the driving clock of the image drawing device, constitutes a restriction on finer drawing.
A burst transfer function is provided to a memory typified by SDRAM in order to release the restriction. More specifically, in the burst transfer mode, each time one address is identified, a predetermined number of data items are continuously accessed from the address in synchronization with the clock. Accordingly, a memory access in the burst transfer mode is much faster than the memory access in the single transfer mode. The advantage of the burst transfer mode is especially remarkable in the drawing process, since the brightness data of pixels aligned in the transverse direction on a screen is usually placed at contiguous address regions in the memory.
In the drawing process, the address of the top or end of the memory region into which image data to be transferred are continuously written (hereinafter, write start address or write end address, respectively) does not generally match with any boundary (hereinafter, a burst boundary) of the unit of the burst transfer (hereinafter, a burst unit). Accordingly, an address at which writing is to be disabled (hereinafter, a write disabled address) is generally included in the burst unit that includes the write start address or the write end address.
In the past, unnecessary writing at the write disabled addresses has been prevented by negating write enable signals for write disabled addresses. However, when a momentarily displayed image is to be slightly shifted, for example, negating the write enable signals for the write disabled addresses may conversely fail to clear a portion of the image and change it to a background. In such cases, there arises a need to newly write the brightness data of the background color at the write disabled addresses preceding the write start address or behind the write end address. This makes it difficult to further reduce the access time of the memory.
The prior art disclosed in Reference 1 is known as a technology to speed up memory access by surmounting this difficulty (cf. FIG. 18). More specifically, write enable signals are first maintained to be asserted throughout a burst unit that includes a write start address or a write end address. Next, background color (e.g., white) brightness data and image data to be placed at write disabled addresses and other addresses included in the burst unit, respectively, are integrated into the same burst unit, and the burst unit is written into the memory. This expedites memory access.
Reference 1: Japan Published Patent Application No. 2002-140702